NANO - STUDENT DESIGN COMPETITIONS (SDC)
All eligible students or student teams are invited to participate in the NANO Student Design Competitions (SDC), held in conjunction with the 26th IEEE International Conference on Nanotechnology (IEEE-NANO 2026) will be held from July 5 – 8, 2026, in Nanjing, China.
The NANO SDC encourages students to employ creative problem solving and gain practical design experience by developing small samples, synthesis and characterization methodologies, novel software, simple prototypes or system to address a problem stated in the competition rules while following specified constraints.
Participants, Requirements & Rules:
- All full-time undergraduate (B.Sc.) and graduate students (M.Sc. & PhD) worldwide are invited to take part in the NANO SDC.
- These students must have an accepted paper/abstract to IEEE NANO 2026.
- Students can form groups of at least 1 member, up to a maximum of 4 members. All team members must be full-time students while working on the project. A student cannot be part of two groups.
- At least one team member must register to the NANO 2026 Conference and attend in person the NANO SDC to assist with presentation, showcase, measurements (where applicable) and answer to judges’ questions.
- To participate in NANO SDC it is necessary to compile a form using the link provided below.
- The deadline is the June 15, 2026.
- Four different topics are given, and students can select only one of the four topics. The students’ project may or may not be directly related to the submitted paper/abstract. In other words, if a student submitted a paper/abstract to IEEE NANO, he/she/them can participate to any topics of the Nano SDC if such a paper/abstract is accepted and registered, independently from the manuscript subject. The students would have time to work on a project to be presented for the NANO SDC until July 2026.
- Students are advised to contact the individual competition organizers as early as possible, to ensure a full understanding of the rules, design specifications and judging criteria before beginning their projects.
- The student must have an academic advisor and he/she/their must certify that the work is completely made by the students.
- The students must notify the Nano SDC organizers at least one week before the date of the competitions if they plan to withdraw or will not be able to participate in person.
- The NANO SDC will take place on July 2026 during a specific public session within the IEEE NANO 2026 Conference, during which they will have to show in 10-15 min their prototypes or software and demonstrate their design outcomes.
- Winners will be recognized during IEEE NANO 2026. Winning teams are awarded with a certificate, recognized at the social dinner, and will have a chance to submit a paper to the IEEE Nanotechnology Magazine for a special session dedicated to the NANO SDC.
Disclaimers:
- Student competitors should be aware that the IEEE NANO 2026 will not assist participants in getting necessary equipment or designed circuits/systems into China.
- Students are responsible for the specific instrumentation needed for the SDCs (e.g., laptop, circuit boards, etc.).
- The students will bring their designs (e.g., software, prototypes, etc.) to the competition where they perform simple measurements or showcase their results and compete against other student teams.
There are different competitions spanning a wide range of topics. Links to descriptions and rules for each competition are below.
N.B.: Travel visas and shipping your project equipment are your responsibility, it is recommended to arrange these as early as possible.
Design Competition Topics
Click the links below to see the individual competition descriptions and rules:
SDC 1-Novel nano communication ways for body area networks (BANs) applications
Introduction
Body area networks (BANs) are pivotal for continuous health monitoring, yet traditional wireless methods (e.g., Bluetooth) face limitations in power, safety, and scalability for deep-tissue applications. Novel nano-communication paradigms—using mechanisms like molecular diffusion, acoustic signaling, or nanoscale electromagnetics—offer transformative potential. These approaches promise superior biocompatibility, minimal power consumption, and high-resolution data exchange within the body, enabling applications from closed-loop neuromodulation to distributed metabolic sensing.
This topic challenges students to design innovative nano-communication architectures for next-generation BANs. Submissions should address feasibility, energy efficiency, and bio-integration, exploring areas such as physical channel modeling, nano-transceiver design, or secure in-body network protocols. The goal is to pave the way for autonomous, personalized healthcare systems.
Design specifications and rules
Participants shall design a proof‑of‑concept nano‑communication system for in‑body BAN applications, demonstrating the feasibility of a defined physical channel. Deliverables must include:
System Architecture: A complete block diagram of the transmitter‑receiver chain, specifying the chosen communication modality (e.g., molecular, acoustic, electromagnetic).
Channel Characterization: Experimental or simulation data quantifying at least two of the following in a tissue‑mimicking environment:
– Path loss (dB) over a distance of 1‑10 mm.
– Data rate (bps) under a BER ≤ 10⁻³.
– Latency (ms) for a 32‑bit packet.
Device Specifications:
– Transmitter power consumption ≤ 100 μW.
– Receiver sensitivity better than ‑70 dBm (for EM schemes) or equivalent.
– Overall module volume ≤ 10 mm³ (excluding external interfaces).
Safety & Compatibility: Evidence of biothermal/cytocompatibility assessment (simulation or literature‑based justification).
Submissions must provide measurable performance data, supported by schematics, test setups, and clear analysis. Designs may be implemented in simulation, hardware, or hybrid form. Emphasis is placed on innovation, quantitative validation, and practical integration within biological constraints.
The final ranking will be determined by a weighted combination of prediction accuracy and reproducibility.
Contact Information
Prof. F. X. Linlin, Tongji University, fxlinlin@tongji.edu.cn
SDC 2-ASIC for prime factoring
Introduction
One can argue that the advantage of emerging nanodevices or of novel architectures compared to the incumbent CMOS digital circuits can be highlighted via non-traditional computing workloads. One of such workloads is factoring integer numbers into prime factors. It is important conceptually since this is one of the NP-hard problems. It is of practical interest, because it leads to breaking popular encryption cyphers.
Design specifications and rules
The participant needs to design an ASIC for factoring any 16-bit integer into prime factors. The participant is free to choose CMOS devices, other traditional or any emerging integrated circuit technology. Devices need to be fabricate-able on a solid-state substrate. The technology does not have to be experimentally demonstrated, but in that case a sufficient amount of simulation work needs to be published to characterize the devices, determine their layout and to compose compact models.
Specifications:
- The design can be digital, analog or mixed.
- The design needs to include: a) the schematic; b) the layout; c) the complete description of a circuit simulation proving the operation of an ASIC for a randomly chosen 10 input numbers.
- The design needs to include at least a 16-bit input register and two 8-bit output registers.
- The input number is assumed to be written into the input register before the operation starts.
- The output factors need to be written into the output registers and read into a set of adjacent state elements.
The figures-of-merit on which the design will be judged are:
- The layout area.
- The overall delay for the operation.
- The dissipated energy for the operation.
which will be obtained from the simulation of the designed circuit.
Caveats:
- The effects of parasitics related to metal wires cannot be reliably estimated for emerging devices and should be neglected.
- For CMOS devices, any publically available compact models for the process node greater than 5nm can be used.
- For other devices the participant can use published compact models with the critical dimension greater than 5nm. Compact models need to be physically justified (i.e. not rely on physically impossible processes).
- The circuit must be able to operate at room temperature.
Some quantitative, detailed specification of the goal that students will attempt to achieve with their design. The specifications may be electrical performance metrics, or might also include other metrics like size, efficiency, etc. All the specification parameters must be measurable. Geography-specific metrics, like fabrication price, etc. are not allowed. (max. 200 words)
Contact Information
Dr. Dmitri Nikonov dmitri@keplercompute.com
Dr. Luiz Felipe Aguinsky luiz.Aguinsky@glasgow.ac.uk
SDC 3-AI-Assisted Design of Nanomaterial Synthesis Protocols from Open Scientific Data
Introduction
The discovery and synthesis of nanomaterials is a key challenge in nanotechnology, with applications ranging from biosensing and photonics to energy and microwave devices. However, identifying optimal synthesis conditions often requires extensive experimental trial-and-error. Recent advances in materials informatics and machine learning enable the extraction of synthesis knowledge from large corpora of scientific publications and open materials databases.
In this topic of the Student Design Competition, participants will develop machine learning or data-driven models capable of predicting synthesis protocols for target nanomaterials using publicly available datasets extracted from scientific literature. The challenge aims to encourage students to explore the intersection of nanotechnology, data science, and artificial intelligence.
Teams will be provided with an open dataset of nanomaterial synthesis procedures (including precursors, temperatures, solvents, and synthesis steps). Based on this information, teams will design algorithms capable of predicting synthesis parameters for a target material composition. Solutions may include machine learning models, physics-informed approaches, or hybrid data-driven methods.
The competition promotes reproducible research, open science, and interdisciplinary skills combining nanotechnology, computational modeling, and artificial intelligence.
Design specifications and rules
Participants must develop a computational tool capable of predicting synthesis parameters for a given target nanomaterial composition.
The competition will use an open dataset of nanomaterial synthesis procedures extracted from scientific literature. The dataset include information such as precursor compounds, synthesis temperatures, reaction steps, and synthesis methods.
The dataset MatSyn25 is available at the following link https://arxiv.org/abs/2510.00776. The dataset contains ~163,240 synthesis procedures, extracted from 85,160 papers and it is focused on 2D materials synthesis. The related paper is avialable here https://arxiv.org/abs/2510.00776.
Each team must submit:
- A trained model or algorithm capable of predicting synthesis conditions
- A short report describing the methodology
- Predicted synthesis protocols for a set of hidden test materials
Performance will be evaluated using quantitative metrics including:
- Precursor prediction accuracy (overlap with literature precursors)
- Temperature prediction error (mean absolute error)
- Synthesis pathway similarity (sequence similarity between predicted and reference procedures)
- Model reproducibility and computational efficiency
Submissions must be fully reproducible using open-source software and publicly available datasets. Teams may use any machine learning approach, including neural networks, graph models, generative models, or physics-informed methods.
The final ranking will be determined by a weighted combination of prediction accuracy and reproducibility.
Contact Information
Name, email address, and phone number of the organizers. In case of SDC originating outside NTC TC, please also provide a contact to a person in supporting NTC TC.
Please submit this form to ieeenanosdc@gmail.com no later than 15th June 2026.
SDC 4-From DFT to Molecular Dynamics: Machine-Learning Interatomic Potential for Electronic Materials
Introduction
The continuing advancement of the nanoelectronic industry has led to the introduction of several novel materials, such as novel semiconductors (e.g., GaN), dielectrics (e.g., HfO2, V2O5), and even 2D materials (e.g., graphene, MoS2). Understanding their structural stability and phase behaviour at the atomistic level is essential for continued device scaling, yet the computational cost of density functional theory (DFT) prohibits the large simulation cells and long timescales required to study realistic device-relevant phenomena.
Machine-learning interatomic potentials (MLIPs) address this gap by learning the DFT energy landscape from a training set of configurations, enabling molecular dynamics at a fraction of the cost. This competition challenges students to execute the full MLIP development workflow for one relevant electronic material of their choice: generating a DFT training dataset through configurational sampling, training an MLIP using an open-source framework, and validating its physical predictions. Students will gain hands-on experience in ab initio simulation, data curation, and modern machine-learning methods for materials modelling — a skill set of growing importance across the nanoelectronics industry and research community.
Design Specifications and Rules
Teams must execute the complete workflow from structural sampling to trained potential. All DFT calculations must be performed using an open-source code (GPAW or Quantum ESPRESSO); all MLIP training using an open-source framework (e.g. MACE, NequIP, or DeePMD). Pre-existing DFT datasets or pre-fitted potentials may not be used. Submissions are assessed on the following measurable criteria:
DFT dataset generation:
Dataset must contain ≥ 300 distinct material configurations, covering at minimum two known crystalline phases, including rattled and strained structures to ensure configurational diversity.
• Each configuration must include DFT total energy, atomic forces, and stress tensor, computed with documented and consistent exchange-correlation functional and k-point settings.
• A train/validation/test split of 70/15/15% must be applied and reported.
MLIP training and validation:
• Energy RMSE on the held-out test set ≤ 10 meV/atom.
• Force RMSE on the held-out test set ≤ 0.15 eV/Å.
• Correct energy ordering of the two chosen crystalline phases at 0 K reproduced by the trained potential.
• Lattice parameters of the monoclinic phase predicted within ±2% of the team’s own DFT reference values.
Physical validation:
A ≥ 10 ps NVT molecular dynamics trajectory at 300 K demonstrating structural stability of the the lowest energy crystalline phase (no phase transition or unphysical bond breaking).
Submissions must include: all DFT input files and outputs, trained model files, a reproducible training script, and a report (max. 6 pages) documenting the sampling strategy, DFT settings, training procedure, validation metrics, and MD results. Teams of 1–4 students; at least one member must be a currently enrolled student.
Contact Information
Dr. Luiz Felipe Aguinsky luiz.Aguinsky@glasgow.ac.uk
Participation Link
To participate in the NANO SDC, click the link below and fill in the form. You will be asked to provide contact information for all team members and your academic advisor, and you will also need to upload a short abstract describing your design approach. In addition, your academic advisor must send an email to the organizers of the competition certifying that the work is yours, not theirs. The application deadline is June 15, 2026.
Students are advised to contact the individual competition organizers as early as possible, to ensure a full understanding of the design specifications and judging criteria before beginning their projects.
Clarification about Student Team Requirements
Teams must consist of at least one and no more than four students. There is no limit to the number of teams that may compete from any given university or organization. However, one student cannot be part of multiple teams.
Submissions are invited from students at all stages of their university careers, from undergraduate to postgraduate level. While not a mandatory requirement, it is strongly encouraged that the teams put forward a multidisciplinary and/or multi-national team.
Whether you were a graduate (i.e., Masters or Doctoral level) or undergraduate (i.e., Bachelor level) when the work was done, or confirm that you are either currently registered in an academic program full-time, or will return to be a student in the upcoming semester.
Contact Information
General questions or comments can be directed to the IEEE NANO 2026 Student Design Competition Committee by writing to ieeenanosdc@gmail.com.
Questions or comments regarding a specific design competition should be directed to the organizers of the competition in question, which will be listed on the competition descriptions.